The present application concerns integrated circuits, especially the structures and processes necessary to integrate dual supply voltages onto a single chip.
Drain Profile Engineering
One of the long-standing problems in submicron field effect transistors is hot carrier effects. In an old-fashioned NMOS single-drain-diffusion transistor structure, the potential energy (voltage) of an electron changes dramatically as it crosses the boundary of the N+ drain diffusion. This sharp change in potential energy, over a short distance, defines a high electric field value, which is undesirable because it causes the electrons (and to a much lesser extent, holes) to behave in a different way within the semiconductor lattice. Electrons which have been activated in this way by high electric fields are referred to as "hot electrons." Such electrons can, for example, penetrate into or through the gate dielectric, and can cause the gate dielectrics to become charged up over time, until the transistor fails in service.
One technique to avoid hot carrier effects is lightly doped drain extension regions, or "LDD" regions. In this structure, a first light and shallow implant is performed before sidewall spacers are formed on the gate structure, with a second heavier implant afterwards to form the source/drain. The first implant provides only a relatively low conductivity in the silicon, but prevents the channel-drain voltage difference from appearing entirely at the drain boundary. By increasing the distance over which this voltage difference occurs, the peak electric field is reduced, and this tends to reduce channel hot carrier ("CHC") effects.
The trade-off as lighter-doped regions are introduced into the process is that transistor performance decreases due to the increased resistance, so the chip designer seeks to find a balance between these two opposing demands. In more recent years, with device sizes shrinking and voltages dropping, the doses needed for LDD regions have become closer to those used for the main source/drain implant, so that these implants are now referred to as "MDD" (medium-doped drain) regions.
Dual-Voltage Chip Architectures
As integrated circuit geometries have shrunk below one micron, the possibility of using two supply voltages has appeared increasingly attractive. In this process option, the central part of a chip (the "core", which performs the actual electrical functionality which is desired from the chip) can be fully optimized for the current state of process engineering for packing density and highest performance, without regard to the voltage standards required for interfacing to the external world. Since many different chips must communicate, the voltage standard required for external interface tend to change relatively slowly. As of 1997, there was no standard signal level below 3.3 volts which is in really widespread usage, whereas the internal voltages of chips in production or announced are very commonly 2.5 volts, 2 volts, or below.
Thus, process optimization for a dual-voltage chip presents some important problems. First, the use of two different voltages demands that different gate oxide thicknesses be used for the core and peripheral transistors. Second, the basic process design should be determined, as far as possible, by optimization of the core devices, since this is the large majority of the area of the chip; the question is then how to modify the basic optimized process to achieve adequate reliability and performance in the peripheral devices. Of course, this must be done while avoiding such problems as CHC effects and punchthrough.
Since each variation between implants received by the core and peripheral transistors requires the use of two separate masks, optimizing both sets of transistors requires 4-5 additional masks, and is not a cost-effective option. However, tests using identical implants for both the low voltage and high voltage devices, while preferable from a fabrication standpoint, do not provide high-voltage transistors which meet the necessary lifetime and performance specifications. The high MDD necessary for the core transistors causes the peripheral transistors to have too high an electrical field, even though the oxide thickness is increased for these transistors. In fact, a 50% reduction in Idrive was required in testing to obtain the desired CFC lifetime specification for this option.
Dual Voltage Process and Structure
The present invention provides a very simple and flexible approach to fabrication and structure of dual-voltage integrated circuits. The inventors have discovered that integration of a dual voltage process can be accomplished by modifying the MDD mask so that the high voltage NMOS device does not receive an MDD implant at all during the formation of the MDD of the low voltage NMOS device, while all other implants remain the same for core and peripheral transistors,thus eliminating the need for extra lithographic steps. The thickness of the sidewall spacer and the conditions of the source/drain implants, both of which are the same for core and peripheral transistors, are adjusted to keep the performance of the high voltage device within specification.
Advantages of the disclosed methods and structures include:
no additional lithographic steps necessary to integrate high-voltage transistors into flow for core transistors.